VHDL顶层

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;

entity shuzi is port ( clk :in std_logic; key1 :in std_logic; key2 :in std_logic; fuc :in std_logic; sss :in std_logic; beep :out std_logic; segout :out std_logic_vector (7 downto 0); count :out std_logic_vector (2 downto 0)); end shuzi;

architecture behave of shuzi is

component counter20M port ( clk :in std_logic; q :out std_logic); end component;

component counter10000 port ( clk :in std_logic; q :out std_logic); end component;

component counter100000 port ( clk :in std_logic; q :out std_logic); end component;

component mux8 port ( d :in std_logic_vector (2 downto 0); din0 :in integer range 0 to 10; din1 :in integer range 0 to 10; din2 :in integer range 0 to 10; din3 :in integer range 0 to 10; din4 :in integer range 0 to 10; din5 :in integer range 0 to 10; din6 :in integer range 0 to 10; din7 :in integer range 0 to 10; segout :out integer range 0 to 10);

end component;

component seg7dec port ( din :in integer range 0 to 10; segout :out std_logic_vector (7 downto 0)); end component;

component counter8 port ( clk :in std_logic; q :out std_logic_vector (2 downto 0)); end component;

component qudou port ( clk :in std_logic; din :in std_logic; q :out std_logic); end component;

component pin1000hz port ( clk :in std_logic; q :out std_logic); end component;

component pin500hz port ( clk :in std_logic; q :out std_logic); end component;

signal clks,clkms,clksms,clkbms,tm,th,tf,ss,beep1,beep2,flag0:std_logic:='0'; signal outs,outss,outm,outsm,outh,outsh:integer range 0 to 11; signal count0:std_logic_vector (2 downto 0); signal segout0:integer range 0 to 10; signal flag:integer range 0 to 2; begin M1:counter20M PORT MAP(clk,clks); M2:counter10000 PORT MAP(clk,clkms); M3:counter100000 PORT MAP(clk,clksms); M4:mux8 PORT MAP(count0,outs,outss,10,outm,outsm,10,outh,outsh,segout0); M5:seg7dec PORT MAP(segout0,segout); M6:counter8 PORT MAP(clkms,count0); M7:qudou PORT MAP(clksms,fuc,tf); M8:qudou PORT MAP(clksms,key1,th); M9:qudou PORT MAP(clksms,key2,tm);

M10:qudou PORT MAP(clkms,sss,ss); M12:pin500hz PORT MAP(clk,beep1); M13:pin1000hz PORT MAP(clk,beep2); count<=count0; beep<=beep1 when outsm=5 AND outm=9 AND outss=5 AND (outs=0 OR outs=2 OR outs=4 OR outs=6 OR outs=8) else beep2 when outsm=0 AND outm=0 AND outss=0 AND outs=0 else '0'; process(tf) begin if rising_edge(tf) then flag0<= NOT flag0; end if; end process; process(clks,th,tm,ss) variable min,sec:integer range 0 to 59; variable hour:integer range 0 to 23; begin if ss='1' then sec:=0; elsif rising_edge(clks) then case flag0 is when '0'=> if sec<59 then sec:=sec+1; else sec:=0; if min<59 then min:=min+1; else min:=0; if hour<23 then hour:=hour+1; else hour:=0; end if; end if; end if; when '1'=> if th='1' then if hour<23 then hour:=hour+1; else hour:=0; end if; end if; if tm='1' then if min<59 then min:=min+1; else hour:=0; end if; end if; end case; end if; outsh<=hour/10;outh<=hour rem 10;outsm<=min/10;outm<=min rem

10;outss<=sec/10;outs<=sec rem 10; end process; end behave; 去抖

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;

entity qudou is port ( clk :in std_logic; din :in std_logic; q :out std_logic); end qudou;

architecture behave of qudou is begin process(clk) variable count:integer range 0 to 2; begin if rising_edge(clk) then if din='0' then q<='0';count:=0; elsif din='1' then if count=2 then q<='1'; else q<='0';count:=count+1; end if; end if; end if; end process; end behave; 分频器 library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;

entity counter20M is port ( clk :in std_logic; q :out std_logic); end counter20M;

architecture bahave of counter20M is signal q0 :std_logic:='0'; begin process(clk) variable count :integer range 0 to 9999999;

begin if rising_edge(clk) then if count<9999999 then count:=count+1; else q0<= NOT q0;count:=0; end if; end if; end process; q<=q0; end bahave;