tlc5615

 TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000D10-Bit CMOS Voltage Output DAC in anDDDDDDDDDDapplications 8-Terminal Package5-V Single Supply Operation3-Wire Serial InterfaceHigh-Impedance Reference InputsVoltage Output Range...2TimestheReference Input VoltageInternal Power-On ResetLow Power Consumption...1.75 mW MaxUpdate Rate of 1.21 MHzSettling Time to 0.5 LSB...12.5 µs TypMonotonic Over TemperaturePin Compatible With the Maxim MAX515DBattery-Powered Test InstrumentsDDigital Offset and Gain AdjustmentDBattery Operated/Remote IndustrialDDControlsMachine and Motion Control DevicesCellular TelephonesD, P, OR DGK PACKAGE(TOP VIEW)DINSCLKCSDOUT12348765VDDOUTREFINAGNDdescriptionThe TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (highimpedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC ismonotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function isincorporated to ensure repeatable start-up conditions.Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced toindustry standard microprocessor and microcontroller devices. The device receives a 16-bit data word toproduce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digitalcommunication protocols include the SPI™, QSPI™, and Microwire™ standards.The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operationfrom –40°C to 85°C.AVAILABLE OPTIONSPACKAGESMALL OUTLINE†PLASTIC SMALL OUTLINE(DGK)(D)TLC5615CDTLC5615IDTLC5615CDGKTLC5615IDGKPLASTIC DIP(P)TLC5615CPTLC5615IPTA0°C to 70°C–40°C to 85°C†Available in tape and reel as the TLC5615CDR and the TLC5615IDRPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI and QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corporation.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 2000, Texas Instruments IncorporatedPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•1SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS functional block diagram_REFIN+DAC+ 2_OUT(Voltage Output)R AGNDPower-ONResetR10-Bit DAC RegisterControlLogic20s(LSB)(MSB)4DummyBitsDOUTCSSCLKDIN10 Data Bits16-Bit Shift RegisterTerminal FunctionsTERMINALNAMEDINSCLKCSDOUTAGNDREFINOUTVDDNO.12345678IOI/OIIIOSerial data inputSerial clock inputChip select, active lowSerial data output for daisy chainingAnalog groundReference inputDAC analog voltage outputPositive power supplyDESCRIPTIONabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDigital input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 VReference input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 VOutput voltage at OUT from external source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 VContinuous current at any terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOperating free-air temperature range, TA:TLC5615C 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 70°CTLC5615I –40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 85°CStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000recommended operating conditionsMINSupply voltage, VDDHigh-level digital input voltage, VIHLow-level digital input voltage, VILReference voltage, Vref to REFIN terminalLoad resistance, RLOperating free-air temperature, TOperatingfreeairtemperatureTATLC5615CTLC5615I4.52.40.8220–4070852.048VDD–2NOM5MAX5.5UNITVVVVkΩ°C°Celectrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,Vref = 2.048 V (unless otherwise noted)static DAC specificationsPARAMETERResolutionIntegral nonlinearity, end point adjusted (INL)Differential nonlinearity (DNL)EZSEGZero-scale error (offset error at zero scale)Zero-scale-error temperature coefficientGain errorGain-error temperature coefficientPSRRPowersupplyrejectionratioPower-supply rejection ratioAnalog full scale outputZero scaleGainVref = 2.048 V,Vref = 2.048 V,Vref = 2.048 V,Vref = 2.048 V,Vref = 2.048 V,Vref = 2.048 V,See Note 1See Note 2See Note 3See Note 4See Note 5See Note 680802Vref(1023/1024)13±3±0.1TEST CONDITIONSMIN10±1±0.5±3TYPMAXUNITbitsLSBLSBLSBppm/°CLSBppm/°CdBVSeeNotes7and8See Notes 7 and 8RL = 100 kΩNOTES:1.The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the outputfrom the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).2.The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remainsconstant) as a change in the digital input code.3.Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).4.Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) – EZS(Tmin)]/Vref × 106/(Tmax – Tmin).5.Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scaleerror.6.Gain temperature coefficient is given by: EGTC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).7.Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion ofthis signal imposed on the zero-code output voltage.8.Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signalimposed on the full-scale output voltage after subtracting the zero-scale change.voltage output (OUT)PARAMETERVOIOSCVOL(low)VOH(high)Voltage output rangeOutput load regulation accuracyOutput short circuit currentOutput voltage, low-levelOutput voltage, high-levelTEST CONDITIONSRL = 10 kΩVO(OUT) = 2 V,RL = 2 kΩOUT to VDD or AGNDIO(OUT) ≤ 5 mAIO(OUT) ≤ –5 mA4.75MIN0200.25TYPMAXVDD–0.40.5UNITVLSBmAVVPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,Vref = 2.048 V (unless otherwise noted) (continued)reference input (REFIN)PARAMETERVIriCiInput voltageInput resistanceInput capacitanceTEST CONDITIONSMIN0105TYPMAXVDD–2UNITVMΩpFdigital inputs (DIN, SCLK, CS)PARAMETERVIHVILIIHIILCiHigh-level digital input voltageLow-level digital input voltageHigh-level digital input currentLow-level digital input currentInput capacitanceVI = VDDVI = 08TEST CONDITIONSMIN2.40.8±1±1TYPMAXUNITVVµAµApFdigital output (DOUT)PARAMETERVOHVOLOutput voltage, high-levelOutput voltage, low-levelIO = –2 mAIO = 2 mATEST CONDITIONSMINVDD–10.4TYPMAXUNITVVpower supplyPARAMETERVDDSupply voltageVDD = 5.5 V,No load,All inputs = 0 V or VDDVDD = 5.5 V,No load,All inputs = 0 V or VDDVref = 0TEST CONDITIONSMIN4.5TYP5150MAX5.5250UNITVµAIDDPowersupplycurrentPower supply currentVref = 2.048 V230350µAanalog output dynamic performancePARAMETERSignal-to-noise + distortion, S/(N+D)TEST CONDITIONSVref = 1 Vpp at 1 kHz + 2.048 Vdc,code = 11 1111 1111,See Note 9MIN60TYPMAXUNITdBNOTE 9:The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.4POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000digital input timing requirements (see Figure 1)PARAMETERtsu(DS)th(DH)tsu(CSS)tsu(CS1)th(CSH0)th(CSH1)tw(CS)tw(CL)tw(CH)Setup time, DIN before SCLK highHold time, DIN valid after SCLK highSetup time, CS low to SCLK highSetup time, CS high to SCLK highHold time, SCLK low to CS lowHold time, SCLK low to CS highPulse duration, minimum chip select pulse width highPulse duration, SCLK lowPulse duration, SCLK highMIN45015010202525NOMMAXUNITnsnsnsnsnsnsnsnsnsoutput switching characteristicPARAMETERtpd(DOUT)Propagation delay time, DOUTCL = 50 pFTEST CONDITIONSMINNOMMAX50UNITnsoperating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,Vref = 2.048 V (unless otherwise noted)analog output dynamic performancePARAMETERSRtsOutput slew rateOutput settling timeGlitch energyCL = 100 pF,TA = 25°CTo 0.5 LSB,RL = 10 kΩ,DIN = All 0s to all 1sTEST CONDITIONSRL = 10 kΩ,CL = 100 pF,See Note 10MIN0.3TYP0.512.55MAXUNITV/µsµsnV󰀀sNOTE 10:Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of000 hex to 3FF hex or 3FF hex to 000 hex.reference input (REFIN)PARAMETERReference feedthroughReference inputbandwidth (f–3dB)TEST CONDITIONSREFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11)REFIN = 0.2 Vpp + 2.048 VdcREFIN = 0.2 Vpp + 2.048 VdcMINTYP–8030MAXUNITdBkHzNOTE 11:Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048 Vdc + 1 Vpp at 1 kHz.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS PARAMETER MEASUREMENT INFORMATIONCSth(CSH0)tsu(CSS)tw(CH) tw(CS)tw(CL)th(CSH1)tsu(CS1)SCLKSee Note Atsu(DS)See Note Cth(DH)See Note ADINtpd(DOUT)DOUTPrevious LSBSee Note BNOTES:A.The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.B.Data input from preceeding conversion cycle.C.Sixteenth SCLK falling edgeMSBLSBFigure 1. Timing Diagram6POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TYPICAL CHARACTERISTICSOUTPUT SINK CURRENTvsOUTPUT PULLDOWN VOLTAGE2018IO – Output Sink Current – mA16141210864200.10.20.30.40.50.60.70.80.911.11.2VDD = 5 VVREFIN = 2.048 VTA = 25°CVO – Output Pulldown Voltage – VFigure 2OUTPUT SOURCE CURRENTvsOUTPUT PULLUP VOLTAGE30VDD = 5 VVREFIN = 2.048 VTA = 25°CIO – Output Source Current – mA252015105054.84.64.44.243.83.63.4VO – Output Pullup Voltage – V3.23Figure 3POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS TYPICAL CHARACTERISTICSSUPPLY CURRENTvsTEMPERATURE280240IDD– Supply Current –µA2001601208040VDD = 5 VVREFIN = 2.048 VTA = 25°C020406080t – Temperature – °C100120140 0–60–40–20Figure 4VREFIN TO V(OUT)RELATIVE GAINvsINPUT FREQUENCY420G – Relative Gain – dB–2–4–6–8–10–12–1411001 k10 k100 kVDD = 5 VVREFIN = 0.2 VPP + 2.048 V dcTA = 25°C7060504030201001 kVDD = 5 VTA = 25°CVREFIN = 4 VPPSIGNAL-TO-NOISE + DISTORTIONvsINPUT FREQUENCY AT REFINSignal-To-Noise + Distortion – dB10 k100 k300 kfI – Input Frequency – HzFrequency – HzFigure 5Figure 68POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TYPICAL CHARACTERISTICSDifferential Nonlinearity – LSB0.20.150.10.050–0.05–0.1–0.15–0.20255511Input Code7671023Figure 7. Differential Nonlinearity With Input Code1Integral Nonlinearity – LSB0.80.60.40.20–0.2–0.4–0.6–0.8–10255511Input Code7671023Figure 8. Integral Nonlinearity With Input CodePOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS APPLICATION INFORMATIONgeneral function The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digitaldata to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is thesame polarity as the reference input (see Table 1).An internal circuit resets the DAC register to all zeros on power up.DINSCLKCSDOUTREFIN+_ResistorStringDAC+_ROUTRAGNDVDD5 V0.1 µFFigure 9. TLC5615 Typical Operating CircuitTable 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2INPUT†11111111:100010000111000000001111:000000000000000001(00)00(00)2V01(00)00(00)11(00)2V2V11(00)2VOUTPUTǒ1023REFIN1024Ǔ:ǒ513REFIN1024Ǔǒ512+VREFIN1024REFIN2VǓǒ511REFIN1024Ǔ:ǒ1REFIN10240 VǓ†A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 valuesmust be written since the DAC input latch is 12 bits wide.10POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000APPLICATION INFORMATIONbuffer amplifierThe output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pFload capacitance. Settling time is 12.5 µs typical to within 0.5 LSB of final value.external referenceThe reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF independent of inputcode. The reference voltage determines the DAC full-scale output.logic interfaceThe logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achievesthe lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logiclevels.serial clock and update rateFigure 1 shows the TLC5615 timing. The maximum serial clock rate is:1f(SCLK)max+tǒǓ)tǒǓwCHwCLor approximately 14 MHz. The digital update rate is limited by the chip-select period, which is:tp(CS)+16 tǒǓ)tǒǓ)tǒǓwCHwCLwCSand is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 µslimits the update rate to 80 kHz for full-scale input step transitions.ǒǓPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•11SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS APPLICATION INFORMATIONserial interface When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in mostsignificant bit first. The rising edge of the SLCK input shifts the data into the input register.The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clockedinto the input register. All CS transitions should occur when the SCLK input is low.If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input datasequence with the MSB first can be used as shown in Figure 10:12 Bits10 Data BitsMSBx = don’t careLSBxx2 Extra (Sub-LSB) BitsFigure 10. 12-Bit Input Data Sequenceor 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.16 Bits4 Upper Dummy BitsMSBx = don’t care10 Data BitsLSBxx2 Extra (Sub-LSB) BitsFigure 11. 16-Bit Input Data SequenceThe data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the datatransfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at theDOUT terminal (see Figure 1).The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit dataconverter transfers.The TLC5615 three-wire interface is compatible with the SPI, QSPI†, and Microwire serial standards. Thehardware connections are shown in Figure 12 and Figure 13.The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to inputdata to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DACinput register in one write cycle.†CPOL = 0, CPHA = 0, QSPI protocol designations12POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000APPLICATION INFORMATIONserial interface (continued)SCLKDINTLC5615CSDOUTSKSOMicrowirePortI/OSISCLKDINTLC5615CSDOUTSCKMOSISPI/QSPII/OPortMISOCPOL = 0, CPHA = 0NOTE A:The DOUT-MISO connection is not required for writing tothe TLC5615 but may be used for verifying data transfer.NOTE A:The DOUT-SI connection is not required for writingto the TLC5615 but may be used for verifying datatransfer if desired.Figure 12. Microwire ConnectionFigure 13. SPI/QSPI Connectiondaisy-chaining devicesDACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device inthe chain, providing that the setup time, tsu(CSS), (CS low to SCLK high) is greater than the sum of the setuptime, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirementssection). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is atotem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high,DOUT remains at the value of the last data bit and does not go into a high-impedance state.linearity, offset, and gain error using single ended suppliesWhen an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. Witha positive offset, the output voltage changes on the first code change. With a negative offset the output voltagemay not change with the first code depending on the magnitude of the offset voltage.The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0 V.The output voltage then remains at zero until the input code value produces a sufficient positive output voltageto overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.OutputVoltage0 VNegativeOffsetDAC CodeFigure 14. Effect of Negative Offset (Single Supply)POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13SLAS142C – OCTOBER 1996 – REVISED MARCH 2000TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS APPLICATION INFORMATIONlinearity, offset, and gain error using single ended supplies (continued) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearityis measured between full-scale code and the lowest code that produces a positive output voltage. For theTLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from themaximum specification for the negative offset.power-supply bypassing and ground managementPrinted-circuit boards that use separate analog and digital ground planes offer the best system performance.Wire-wrap boards do not perform well and should not be used. The two ground planes should be connectedtogether at the low-impedance power-supply source. The best ground connection may be achieved byconnecting the DAC AGND terminal to the system analog ground plane making sure that analog groundcurrents are well managed and there are negligible voltage drops across the ground plane.A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leadsas close as possible to the device. Use of ferrite beads may further isolate the system analog supply from thedigital power supply.Figure 15 shows the ground plane layout and bypassing technique.Analog Ground Plane123487650.1 µFFigure 15. Power-Supply Bypassingsaving powerSetting the DAC register to all 0s minimizes power consumption by the reference resistor array and the outputload when the system is not using the DAC.ac considerationsdigital feedthroughEven with CS high, high-speed serial data at any of the digital input or output terminals may couple through theDAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digitalfeedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.analog feedthroughHigher frequency analog input signals may couple to the output through internal stray capacitance. Analogfeedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied toREFIN, and monitoring the DAC output.14POST OFFICE BOX 655303 DALLAS, TEXAS 75265• TLC5615C, TLC5615I10-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS142C – OCTOBER 1996 – REVISED MARCH 2000MECHANICAL DATAD (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0.050 (1,27)0.020 (0,51)0.014 (0,35)1480.008 (0,20) NOM0.244 (6,20)0.228 (5,80)0.157 (4,00)0.150 (3,81)0.010 (0,25)MGage Plane0.010 (0,25)1A70°–8°0.044 (1,12)0.016 (0,40)Seating Plane0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)0.004 (0,10)PINS **DIMA MAX80.197(5,00)0.189(4,80)140.344(8,75)0.337(8,55)160.394(10,00)0.386(9,80)4040047/D 10/96A MINNOTES:A.B.C.D.All linear dimensions are in inches (millimeters).This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).Falls within JEDEC MS-012POST OFFICE BOX 655303 DALLAS, TEXAS 75265•15MPDI001A – JANUARY 1995 – REVISED JUNE 1999MECHANICAL DATA P (R-PDIP-T8)0.400 (10,60)0.355 (9,02)85 MECHANICAL DATAPLASTIC DUAL-IN-LINE0.260 (6,60)0.240 (6,10)140.070 (1,78) MAX0.325 (8,26)0.300 (7,62)0.015 (0,38)0.200 (5,08) MAXSeating Plane0.125 (3,18) MIN0.010 (0,25) NOMGage Plane0.020 (0,51) MIN0.100 (2,54)0.021 (0,53)0.015 (0,38)0.010 (0,25)M0.430 (10,92)MAX4040082/D 05/98NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Falls within JEDEC MS-001For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm16POST OFFICE BOX 655303 DALLAS, TEXAS 75265• MPDI001A – JANUARY 1995 – REVISED JUNE 1999MECHANICAL DATA MECHANICAL DATADGK (R-PDSO-G8) 0,380,2585PLASTIC SMALL-OUTLINE PACKAGE0,650,25M0,15 NOM3,052,954,984,78Gage Plane0,2513,052,9540°–6°0,690,41Seating Plane1,07 MAX0,150,050,104073329/B 04/98NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion.Falls within JEDEC MO-187For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htmPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•17IMPORTANT NOTICE

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