FUJITSU SEMICONDUCTORDATA SHEETDS04-21330-1EASSPSingle Serial InputPLL Frequency SynthesizerOn-Chip 2.0GHz PrescalerMB15E05sDESCRIPTIONThe Fujitsu MB15E05 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.0 GHz prescaler. A/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6mA typ. Thisoperates with a supply voltage of 3.0V (typ.).Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result ofthis, MB15E05 is ideally suitable for digital mobile communications, such as PCN (Personal Communication Network),PCS (Personal Communication Service), etc.sFEATURES•••••••High frequency operation: 2.0 GHz maxLow power supply voltage: VCC = 2.7 to 3.6VVery Low power supply current : ICC = 6.0 mA typ. (Vcc = 3V)Power saving function : IPS = 10 µA max.Pulse swallow function: /65 or 128/129 Serial input 14-bit programmable reference divider: R = 5 to 16,383Serial input 18-bit programmable divider consisting of:- Binary 7-bit swallow counter: 0 to 127- Binary 11-bit programmable counter: 5 to 2,047•Wide operating temperature: Ta = –40 to 85°C•Plastic 16-pin SSOP package (FPT-16P-M05)sPACKAGE 16-pin, Plastic SSOP(FPT-16P-M05)This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.1元器件交易网www.cecb2b.com
MB15E05
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PIN ASSIGNMENT
OSCinOSCout
VpVccDoGNDXfinfin
1234
161514
φRφP
LD/foutZCPSLEDataClock
TOP13VIEW512678
11109
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MB15E05
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PIN DESCRIPTIONS
Pin No.1
Pin NameOSCIN
I/OI
Descriptions
Programmable reference divider input.Oscillator input.
Connection for an crystal or a TCXO.
TCXO should be connected with a coupling capacitor. Oscillator output.
Connection for an external crystal.
Power supply voltage input for the charge pump. Power supply voltage input.
Charge pump output.
Phase of the charge pump can be reversed by FC input.Ground.
Prescaler complementary input, and should be grounded via a capacitor.Prescaler input.
Connection with an external VCO should be done with AC coupling.Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.)Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)Control bit = ”H” ; Data is transmitted to the programmable reference
counter.
Control bit = ”L” ; Data is transmitted to the programmable counter.Load enable signal input (Open is prohibited.)When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data.
Power saving control input. This pin should be set at ”L” at Power-ON. (Open is prohibited.)PS = ”H” ; Normal mode
PS = ”L” ; Power saving mode
Forced high-impedance control for the charge pump (with internal pull up resistor.)
ZC = ”H” ; Normal Do output.
ZC = ”L” ; Do becomes high impedance.
Lock detect signal output(LD)/ phase comparator monitoring output (fout).
The output signal is selected by LDS bit in the serial data.LDS = ”H” ; outputs fout (fr/fp monitoring output)
LDS = ”L” ; outputs LD (”H” at locking, ”L” at unlocking.)Phase comparator output for an external charge pump.Phase comparator output for an external charge pump.
234567
OSCOUT
VPVCCDOGNDXfinfinClock
O––O–III
10DataI
11LEI
12PSI
13ZCI
14LD/foutO
1516
φPφR
OO
3
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MB15E05
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BLOCK DIAGRAM 1
OSCIN1frCrystal Oscillator circuitOSCOUT2fpProgrammablereference dividerBinary 14-bitreference counterfrLDPhasecomparator16φR15φPLockdetectorPS12Intermittent mode control(power save)LESWLDSFC17-bit latch14-bit latch3-bit latchLD/fr/fpselectorfp14LD/foutLE111-bitcontrol latch19-bit shift registerCNTChargepump13ZC3VPData1019-bit shift registerClock9Super chargerLE5DO18-bit latch7-bit latch11-bit latchSWProgrammable dividerXfIN7fIN8Prescaler/65, 128/129Binary 7-bit Binary 11-bit swallow programmablecounter counterfpGND6VCC4MDControl Circuit4
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MB15E05
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ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltageInput voltageOutput voltageStorage temperature
SymbolVCCVPVIVOTstg
Rating–0.5 to +4.0VCC to +6.0–0.5 to VCC +0.5–0.5 to VCC +0.5–55 to +125
UnitVVVV°C
Remark
Note:Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
Parameter
SymbolVCCVPVITa
Value
Min2.7VCCGND–40
Typ3.0–––
Max3.66.0VCC+85
UnitVVV°C
Remark
Power supply voltageInput voltage
Operating temperature
Notes:To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
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MB15E05
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ELECTRICAL CHARACTERISTICS
Parameter
SymbolICC
ConditionfinIF =
2000MHz, fosc = 12MHzVcc current atPS =”L” and ZC = ”H”min. 500mVp-p50Ω termina-tion (Refer to the test circuit.)
Value
Min–
Typ6.0
Max–
UnitmA
Power supply current*
1
Power saving current*Operating frequency
2
IpsfinfOSCVfinIFVOSCVIHVILIIHIILIIHIILIIHIILVOLVOHVOLVDOHVDOLIOFFIOLIOHIOLIDOH
Do
IDOL
–1003–10500Vccx0.7––1.0–1.0–1.0
–––––––––––––––––––––––10.0*2
10200040+2VCC–Vccx0.3+1.0+1.0+1.00+10000.4–0.4–0.41.1––1.0––
µAMHzMHzdBmmVp–pV
Crystal oscillator operating frequencyInput sensitivity
finOSCin
Input voltage
Data, Clock,
LE, PS, ZCData, Clock,LE, PS
Input current
ZCOSCinφP
Output voltage
φR,LD/foutDo
High impedancecutoff current
DoφPφR,LD/fou
Output current
µAµAµAVVVµAmAmA
Pull up input–1000–100
Open drain output
–Vcc-0.4–Vcc-0.4––
Open drain output
1.0–1.0
Vcc = 3.0V, Vp = 5V,VDOH = 4.0VVcc = 3.0V, Vp = 5V, VDOL = 1.0V
–
mA
–
10.0*2
–
*1:Conditions ; Vcc = 3.0V, Ta = 25°C, in locking state.*2:Conditions ; Ta = 25°C6
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MB15E05
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FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO:Output frequency of external voltage controlled oscillator (VCO)N:Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)A:Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)fOSC:Output frequency of the reference frequency oscillatorR:Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)M:Preset divide ratio of modules prescaler ( or 128)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable referencedivider and the programmable divider separately.Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
HL
Destination of serial data
17 bit latch (for the programmable reference divider)18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference CounterLSB1CNTCNTR1 to R14SWFCLDS2R13R24R35R46R5Data FlowMSB7R68R79R810R911R1012R1113R1214R1315161718R14SWFCLDS: Control bit: Divide ratio setting bit for the programmable reference counter (5 to 16,383): Divide ratio setting bit for the prescaler (/65 or 128/129): Phase control bit for the phase comparator: LD/fout signal select bit[Table. 1][Table. 2][Table. 5][Table. 7][Table. 6]Note: Start data input with MSB first 7
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MB15E05
Programmable Reference CounterLSB1CNTCNT: Control bitN1 to N11: Divide ratio setting bits for the programmable counter (5 to 2,047)A1 to A7: Divide ratio setting bits for the swallow counter (0 to 127)Note: Start data input with MSB first [Table. 1][Table. 3][Table. 4]2A13A24A35A46A57A68A7Data FlowMSB9N110N211N312N413N514N615N716N817N918N1019N11Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divideratio(R)56⋅16383
R1400⋅1
R1300⋅1
R1200⋅1
R1100⋅1
R1000⋅1
R900⋅1
R800⋅1
R700⋅1
R600⋅1
R500⋅1
R400⋅1
R311⋅1
R201⋅1
R110⋅1
Note:• Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divideratio(N)56⋅2047
N1100⋅1
N1000⋅1
N900⋅1
N800⋅1
N700⋅1
N600⋅1
N500⋅1
N400⋅1
N311⋅1
N201⋅1
N110⋅1
Note:• Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
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MB15E05
Table.4 Binary 7-bit Swallow Counter Data Setting
Divideratio(A)01⋅127
A700⋅1
A600⋅1
A500⋅1
A400⋅1
A300⋅1
A200⋅1
A101⋅1
Note:• Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SWHL
Prescaler Divide ratio
/65128/129
Table. 6 LD/fout Output Select Data Setting
LDSHL
fout signalLD signal
LD/fout output signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = ”H”)
FC = High
Do
fr > fp
H
fr < fp Lfr = fp Z** :High impedance
φRLHL
φPLZ*Z*
LD/fout(fr)(fr)(fr)
DoLHZ*
HLL
FC = LowφR
φPZ*LZ*
LD/fout(fp)(fp)(fp)
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MB15E05
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
∗:When the LPF and VCO characteristics are similar to x , set FC bit high.∗:When the VCO characteristics are similar to y, set FC bit low.VCO OutputFrequencyPLLLPFVCOLPF Input VoltagexyPower Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to10µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power savingmode. In general, the power consumption can be saved by the intermittent operation that powering down or wakingup the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signalis unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency(fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detectorduring power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power savingfunction stops working, then current consumption is reduced to 10µA per one PLL section.
At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes highimpedance.
A VCO control voltage is naturally kept at the locking voltage which defined by a LPF”s time constant. As a resultof this, VCO’s frequency is kept at the locking frequency.
Note:•While the power saving mode is executed, ZC pin should be set at ”H” or open. If ZC is set at ”L”during power saving mode, approximately 10 µA current flows.•PS pin must be set ”L” at Power-ON.•The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.•During the power saving mode, it is possible to input the serial data.Table.8 PS Pin Setting
PS pinHL
Normal modePower saving mode
Status
Table.9 ZC Pin Setting
ZC pinHL
Do output
Normal outputHigh impedance
10
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MB15E05
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SERIAL DATA INPUT TIMING
DataMSBLSBClockLEt2t1t7t5t3t6t4On rising edge of the clock, one bit of the data is transferred into the shift register.Parametert1t2t3t4Min.20203020Typ.––––Max.––––UnitnsnsnsnsParametert5t6t7Min.30100100Typ.–––Max.–––Unitnsnsns11
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MB15E05
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PHASE COMPARATOR OUTPUT WAVEFORM
frfptWULD[ FC = ”H” ]tWLφPφRHDoZL[ FC = ”L” ]φPφRHDoLZNotes:1.Phase error detection range: –2π to +2π2.Pulses on Do output signal during locked state are output to prevent dead zone.3.LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cysles or more.4.tWU and tWL depend on OSCin input frequency.tWU > 8/fosc (e. g. tWU > 625ns, foscin = 12.8 MHz)tWL < 16/fosc (e. g. tWL < 1250ns, foscin = 12.8 MHz)5.LD becomes high during the power saving mode (PS = ”L”.) 12
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MB15E05
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TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCC VP 0.1µ1000pP • G50 Ω1000p8763210.1µ50 Ω1000pP • G910111213141516OscilloscopeController (setting divide ratio)Vcc13
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MB15E05
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APPLICATION EXAMPLE
LPF10k12k12kVCOOutputTo a lock detect.10kFroma controllerφR1615φPLD/FOUTZC1413PS12LE11Data109Clock MB15E051OSCIN2OSCOUT3VP4VCC5DO6GND7XfIN1000pX’ talC1C20.1µ0.1µ8fIN1000pC1, C2:Depend on the crystal parameters14
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MB15E05
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TYPICAL CHARACTERISTICS
Do Output Current[Ta = +25°C][VCC = 3 V, Vp =3 V, 5 V]5.04.0VOH (V)VOL (V)3.02.01.000–5–10IOH (mA)–15–20Vp = 3 VVp = 5 V[Ta = +25°C][VCC = 3 V, Vp =3 V, 5 V]5.04.03.02.01.000510IOL (mA) 15 20Vp = 3 VVp = 5 Vfin Input SensitivityVfin vs. fin[Ta = +25°C]+100Main. counter div. ratio = 4104Swallow=\"ON\"VCC = VpSPECVfin (dBm)–10–20–30–4001000VCC=2.7 VVCC=3.0 VVCC=3.6 VOSCin Input CharacteristicsVfiosc vs. fosc[Ta = +25°C]+100Vfosc (dBm)–10–202000fin (MHz)30004000Ref. counter div. ratio = 767fin, Xfin : OPENSPECVCC=2.7 V–30–40050100150VCC=3.0 VVCC=3.6 Vfosc (MHz)200(Continued)15
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MB15E05
(Continued) fin Input Impedance
4: 18.13 Ω 14.6 Ω1.1669 nH
2 000.000 000 MHz
1: 19.508 Ω
–124.4 Ω500 MHz
4
2: 10.139 Ω
–47.135 Ω
1 GHz3: 10.783 Ω
–11.995 Ω1.5 GHz
3
12fin
OSCin Input Impedance
3: 484.25 Ω –2.8518 kΩ2.7905 pF
20.000 000 MHz
1: 28.348 kΩ
–19.661 kΩ
1 MHz2: 593.25 Ω
–5.615 kΩ10 MHz4: 152.56 Ω
–1.2722 kΩ
50 MHz
OSCin
3124
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MB15E05
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REFERENCE INFORMATION
Typical plots measured with thetest circuit are shown below.Each plot shows lock up time,phase noise and referenceleakage.Test CircuitS.GOSCinDofinLPF•••••fvco = 1835 MHzKv = 87 MHz/vfr = 200 kHzfosc = 13 MHzLPF:
15 kΩ910 ΩSpectrumAnalyzerVCO3000 pF0.03 µF400 pFPLL Lock Up Time = 500 µs(1797.6 MHz → 1872.4 MHz, within ± 1kHz)∆ MKr x : 500.01844 µsy : –74.8009 MHz38.00500MHzREF10dB/ PLL Phase Noise@ within loop band = 69.4 dBc/Hz0.0 dBmATT 10 dB2.000kHz/divRBW300 HzVBW300 Hz18.1339 µs1.9903829 msSPAN 50.0 kHzCENTER 1.8350000 GH z29.99500MHz∆ MKr x : 500.01844 µsy : –74.8009 MHz250.0000MHzREF10dB/50.00000MHz/div PLL Reference Leakage@ 200 kHz offset = 74.6 dBc0.0 dBmATT 10 dB0Hz18.1339 µs1.9903829 msRBW10 kHzVBW10 kHzSPAN 1.00 MHzCENTER 1.8350000 GHz17
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MB15E05
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ORDERING INFORMATION
Part numberMB15E05PFV1
Package16-pin Plastic SSOP(FPT-16P-M05)
Remarks
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MB15E05
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PACKAGE DIMENSION
16 pins, Plastic SSOP(FPT-16P-M05)* : These dimensions do not include resin protrusion.*5.00±0.10(.197±.004)1.25+0.20–0.10.049+.008–.0040.10(.004)INDEX*4.40±0.106.40±0.205.40(.213)(.173±.004)(.252±.008)NOM0.65±0.120.22+0.10\"A\"+0.05–0.050.15–0.02Details of \"A\" part(.0256±.0047).009+.004–.002.006+.002–.0010.10±0.10(.004±.004)(STAND OFF)4.55(.179)REF0 10°0.50±0.20(.020±.008)C1994 FUJITSU LIMITED F16013S-2C-4Dimensions in mm (inches)19
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FUJITSU LIMITEDFor further information please contact:JapanFUJITSU LIMITEDCorporate Global Business Support DivisionElectronic DevicesKAWASAKI PLANT, 4-1-1, KamikodanakaNakahara-ku, Kawasaki-shiKanagawa 211-88, JapanTel: (044) 7-3763Fax: (044) 7-3329North and South AmericaFUJITSU MICROELECTRONICS, INC.Semiconductor Division35 North First StreetSan Jose, CA 95134-1804, U.S.A.Tel: (408) 922-9000Fax: (408) 432-9044/9045EuropeFUJITSU MIKROELEKTRONIK GmbHAm Siebenstein 6-1063303 Dreieich-BuchschlagGermanyTel: (06103) 690-0Fax: (06103) 690-122Asia PacificFUJITSU MICROELECTRONICS ASIA PTE. LIMITED#05-08, 151 Lorong ChuanNew Tech ParkSingapore 556741Tel: (65) 281-0770Fax: (65) 281-0220F9703© FUJITSU LIMITED Printed in JapanAll Rights Reserved.
The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.
The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
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